This is a quick start tutorial designed to show how to get started using BeetleboxCI and Vitis AI, in which we will cover the following:
The accompanying git repository for this tutorial may be found here.
A beginners guide to getting started with AI on FPGAs for embedded systems. This tutorial uses Xilinx Zynq series FPGAs and the Xilinx Vitis AI tool as well as Tensorflow and Keras. The tutorials accompanying this code can be found on the Beetlebox website or on our github.io:
The tutorials are focused on Sign Language recognition using Vitis AI to translate models built in Tensorflow and Kaggle, explaining both the theory of why and how we use FPGAs for AI and the practise of implementing it. The dataset was chosen because it is small enough to allow for quick training on CPUs. This is the second in a multi-part series, but is also the perfect place to begin:
This tutorial uses the Sign Language MNIST dataset from Kaggle. It consists of the alphabet represented in American Sign Language (excluding J and Z which require motion to represent). It is designed as a drop-in replacement of the famous MNIST dataset and uses the same 28×28 pixel format with 27,455 cases for training and 7172 cases for testing.
Let’s get our AI up and running on BeetleboxCI within five minutes.
sign-language-mnist
.git clone https://github.com/beetleboxorg/sign_language_mnist.git
cd sign_language_mnist
git push --mirror git@github.com:<yourgitaccount>/sign-language-mnist.git
cd ..
rm -rf sign_language_mnist
Add Project
.sign-language-mnist
listed in our repository. Click the button labelled Create Project
Artifact Store
and click the button labelled Upload your first artifact
.archive.zip
. Do not unzip it. Give the file the artifact type of Miscellaneous
. Wait for the file to finish uploading, where you should be taken back to the Artifact Store:In twelve simple steps, we have setup our code and data, trained our neural network, converted the model and prepared for use on a FPGA, all on a single pipeline.
Once we have downloaded our model from BeetleboxCI, we then need to set up our FPGA. To do this we first need to flash an image containing all the hardware we need onto the FPGA. Fortunatly, Xilinx provides a pre-made one and instructions on how to flash an image in the Vitis User Guide found here.
We need to ensure we can successfully boot and connect to the FPGA using SSH as outlined in the user guide. This may involve configuring the boards IP through ifconfig:
ifconfig eth0 192.168.1.10 netmask 255.255.255.0
We then need to copy the files over that we generated in the deploy folder
scp <Cloned-directory>/sign_language_mnist/deploy root@192.168.1.10:~/
Finally we can run the file:
cd deploy
python3 sign_language_app.py --model sign_language_mnist.xmodel --image_dir images --threads 1 -s ./test_resultguide.json
We should see a result like so:
Throughput: 1045.72 FPS
Custom Image Predictions:
Custom Image: test_b Predictions: U
Custom Image: test_c Predictions: F
testimage_9.png Correct { Ground Truth: H Prediction: H }
testimage_6.png Correct { Ground Truth: L Prediction: L }
testimage_5.png Correct { Ground Truth: W Prediction: W }
testimage_1.png Correct { Ground Truth: F Prediction: F }
testimage_2.png Correct { Ground Truth: L Prediction: L }
testimage_7.png Correct { Ground Truth: P Prediction: P }
testimage_4.png Correct { Ground Truth: D Prediction: D }
testimage_3.png Correct { Ground Truth: A Prediction: A }
testimage_0.png Correct { Ground Truth: G Prediction: G }
testimage_8.png Correct { Ground Truth: D Prediction: D }
Correct: 10 Wrong: 0 Accuracy: 100.00