Over at Beetlebox we are excited for the release of Vitis, which is the unification of all of Xilinx’s previous software into a single package. We have been working hard on computer vision using this platform and thought that we could provide some help to others wanting to get started on Xilinx’s development boards. This tutorial will be a multi-part series covering the basics of getting started with computer vision and Vitis and will be covering:
We hope these tutorials will be useful for anyone looking to get into computer vision on FPGAs.
In our previous tutorial, we looked at building the platform project with Linux and XRT and then we built an example application project in hardware and ran it. Running through this process, it is hard not to notice that building the hardware was incredibly slow and that was just for a simple project.
Thankfully Vitis provides ways of emulating our application projects to increase the speed at which we can build and test them. The Vitis Development Flow involves moving from emulation to running on hardware. In this tutorial, we will explore all three methods:
In software emulation, both the host and kernel code is compiled quickly to run on an x86 system. Running our application requires the use of Linux, so Vitis will use the Quick EMUlator (QEMU) to run a Linux system (more information can be found here) and our application will then run on this emulator. This is the best mode for basic application testing and debugging and should be as the starting point for an project.
Hardware emulation runs the host code on a simulator as before, but the kernel code is compiled into RTL code and then runs on the Vivado simulator, providing a cycle accurate view of the kernel code. This is useful for checking if there are any differences between software and hardware functionality and also provides us with performance estimates for our kernel.
Hardware mode provides us with the files we need to run the system on our embedded platform with the host code running on the ARM processors and the kernels being placed onto the FPGA fabric itself. This effectively creates the ‘release’ version of our system.
Pre-requisites:
Our particular setup:
To show the differences between the three build modes, we need code that contains both host and kernel code. Vitis provides us with an example program that performs vector addition, so we will use that. Let us begin with a new application program:
std::cout << "Hello World from Beetlebox"<< std::endl;
Now that we have modified the code we need to ensure it is functionally correct:
Hello World from Beetlebox Loading: './binary_container_1.xclbin' TEST PASSED
cd /mnt ./app_1.exe binary_container_1.xclbin
Since our code now works in Software Emulation, we need to ensure that the hardware will have the same behaviour through Hardware Emulation.
Hello World from Beetlebox Loading: './binary_container_1.xclbin' TEST PASSED
Now that we have ensured correct functionality, it is finally time to deploy our program on hardware.
cd /mnt ./app_1.exe binary_container_1.xclbin
Hello World from Beetlebox
Loading: './binary_container_1.xclbin'
TEST PASSED
Using a 'Hello World' example from Vitis, we have gone through the basic Vitis Development Flow process. Using this, we can now develop our own applications in a manner which is efficient to debug.
Previous: Getting XRT and PetaLinux working on Xilinx boards
Next: Running an OpenCV Application Program in Vitis
If you have enjoyed this tutorial but are in current need of talent to build advanced Computer Vision systems on FPGAs, consider joining our ClickCV Early Access programme. ClickCV Early Access provides bespoke service and support for developing advanced Computer Vision systems on FPGAs. We use our own proprietary Computer Vision Library, ClickCV, to provide our clients the cutting edge in low latency, high performance processing. Contact us today to find out how we could build your next-generation system.
About the Author: Andrew Swirski is the founder and managing director of Beetlebox, a Computer Vision Acceleration specialist. The company develops the Computer Vision Acceleration library called ClickCV, which is designed to fully utilise the hardware adaptability and performance of FPGA chips. Beetlebox is currently running an Early Access programme, where the company provides bespoke service and support to develop client’s Computer Vision systems on FPGAs. Before Beetlebox, Andrew Swirski previously worked at Intel (formerly Altera) in FPGA encoding and decoding. He completed a Masters’ in Electrical and Electronic Engineering from Imperial College London in 2017.
6 Comments
Bobb Piatek
Excellent tutorial. Well written and documented with images.
Vitis is familiar to previous tools but different enough that lots of people are having difficulty making the jump. Thanks, Andrew, for helping us come up to speed with Vitis.
Eager to see the next tutorials in the series.
Bob
Bartokon
When will we get part 3? 🙂
Andrew Swirski
Up now:
https://beetlebox.org/getting-started-with-computer-vision-for-vitis-embedded-systems-part-3-using-opencv-and-file-transfers/
Angel
Hi, I’m new at xilinx and Linux. Ans xilinx’s platform said that I’m need 18.04.04 but always upgrade to 18.04.05. How prepare I the Ubuntu tu install vitis.
Angel
Hi, I’m new at xilinx and Linux. Ans xilinx’s platform said that I’m need 18.04.04 but always upgrade to 18.04.05. How prepare I the Ubuntu tu install vitis.
Dat Phung
When I run the Hardware Emulation, Vivado pops up and have an error:
“……/Emulation-HW/_vimage/rundir/behav_waveform/xsim/libdpi.so:undefined symbol:_ZTI14remoteport_tim
ERROR:[Simtcl 6-50]Simulation engine failed to start: Simulation exited with status code 127. Please see the TCL Console or the Messages for details”
And the simulation is failed.
Have you any solutions to fix it ?
Please help me ! Thank you very much !
Best Regards,
Dat Pt