The Beetlebox Design Suite is the first Mid-Level Synthesis tool and language
The expressibility of a Hardware Description Language
The Beetlebox compiler is built for design space exploration
The usability of a High Level Synthesis tool
Approachable for engineers new to IP design and easy to learn for veterans
Designed for FPGAs
We have designed the language from the ground-up to fully utilise the potential of FPGAs
Current FPGA Hardware Description Languages (HDLs) are slow to develop for and difficult to debug. The industry has tried to respond to this issue by developing High Level Synthesis (HLS) tools, using languages intended for processor programming, such as C/C++. Since these languages were never meant for use on FPGAs, it is difficult to effectively utilise them.
We are developing a new tool and language for FPGAs, combining the strengths of HDL and HLS tools. We allow for the large design space exploration and parallelism of HDL, whilst keeping the approachability of HLS tools, allowing for fast and easy IP development.